Journal Papers

  1. Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama and Michitaka Kameyama, "Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators", IEICE Transaction on Fundamentals, Vol.E98-A,No.12,pp.2658-2669(2015)
  2. Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yasuhiro Takei, and Michitaka Kameyama, "FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation," Journal of Computational Engineering, vol. 2014, Article ID 634269, (2014). doi:10.1155/2014/634269
  3. Zhengfan Xia, Masanori Hariyama, and Michitaka Kameyama, "Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path", IEEE Transaction on VLSI Systems, Vol.23, No. 4, pp.619-630(2015). doi:10.1109/TVLSI.2014.2314685
  4. Yasuhiro Takei, Hasitha Muthumala WAIDYASOORIYA, Masanori Hariyama, Michitaka Kameyama, "Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators", IEICE Transaction on Information and Systems, Vol.E96-A,No.12,pp.2576-2586 (2013)
  5. Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama, "Architecture of an Asynchronous FPGA for Handshake-Component-Based Design", IEICE Transaction on Information and Systems, Vol.E96-D, No.8, pp.1632-1644(2013)
  6. SHOTA ISHIHARA, NORIAKI IDOBATA, MASANORI HARIYAMA AND MICHITAKA KAMEYAMA, "Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures", Journal of Multiple-Valued Logic and Soft Computing, Vol.20, No.5-6, pp.595-623(2013)
  7. Yoshitaka HIRAMATSU, Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Toru NOJIRI, Kunio UCHIYAMA, and Michitaka KAMEYAMA, "Acceleration of Block Matching on a Low-power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-allocation", IEICE Trans. Elec. VOL.E95-C,No.12, pp.1872-1882,No.(2012)
  8. Masanori HARIYAMA, Hasitha muthumala waidyasooriya, Yasuhiro TAKEI, and Michitaka KAMEYAMA, "Platform and Mapping Methodology for Heterogeneous Multicore Processors", Interdisciplinary Information Sciences, Vol. 18, No. 2,pp.175-184 (2012)
  9. Xia Zhengfan, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama,"Design of High-performance Asynchronous Pipeline Using Synchronizing Logic Gates", IEICE Transaction on Electron,VOL.E95-C, No.8, pp.1434-1443(2012)
  10. Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama, "Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors",IEICE Trans. Inf. and Syst.,Vol.E95-D, No.2,pp.354-363(2012)
  11. Shota ISHIHARA Ryoto TSUCHIYA Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA, "Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture", IEICE Transaction on Electron., Vol.E-94-C, No.10, pp.1669-1679, October(2011)
  12. Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama,and Michitaka Kameyama, "Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors", IEEE Transactions on Circuits and Systems for Video Technology, Vol.21, No. 10, pp.1453-1466 (2011) 48.Shota Ishihara, Masanori Hariyama, Michitaka Kameyama, "A Low-Power FPGA Based on Autonomous Fine-Grain Power　Gating", IEEE Transactions on Very Large Scale Integration Systems, Vol. 19, No. 8, pp.1394-1406 (2011)
  13. Shota Ishihara, Noriaki Idobata, Yoshihiro Nakatani, Masanori Hariyama and Michitaka Kameyama, "A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals", Journal of Multiple-Valued Logic and Soft Computing, Vol. 17, No.5-7, pp.553-580(2011)
  14. Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama, "Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions", IEICE Transaction on Fundamentals, Vol.E94-A,No.1,pp.pp.342-351(2011)
  15. Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama, "Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation", IEICE Transaction on Fundamentals, VOL. E93-A, No. 12(2010)
  16. Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama,"Evaluation of a Self-Adaptive Voltage Control Scheme for Low-Power FPGAs",Journal of Semiconductor Technology and Science (JSTS), Vol. 10, No. 3, pp.165-175, 2010.
  17. Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama, "An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture", IEICE Transactions on Electronics, Vol. E93-C, No. 8(Aug.),pp.1338-1348(2010)
  18. Shota Ishihara, Noriaki Idobata, Masanori Hariyama,Michitaka Kameyama, "A Switch Block Architecture for Multi-Context FPGAs Based on Ferroelectric-Capacitor Functional Pass- Gate Using Multiple/Binary Valued Hybrid Signals", IEICE Transaction on Information and Systems, Vol. E93-D, No. 8(Aug.), pp.2134-2144(2010)
  19. Z. Xia, S. Ishihara, M. Hariyama, M. Kameyama, "Synchronising logic gates for wave-pipelining design", Electronics Letters, Vol. 46, No. 16, pp. 1116-1117(2010).
  20. Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA and Michitaka KAMEYAMA, "Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture", IEICE Transaction on Electron., Vol.E92-C, No.4, pp.539-549(2009)
  21. Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyamaa, "Optimal Periodic Memory Allocation for Image Processing with Multiple Windows", IEEE Trans. VLSI Systems, Vol.17, No, 3, pp.403-416(2009)
  22. Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA and Michitaka KAMEYAMA, "Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages", IEICE Transaction on Fundamentals, VOL.E91-A, No12, pp.3596-3606(2008)
  23. Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama, "Memory Allocation for Multi-Resolution Image Processing", IEICE Transaction on Information and Systems, Vol.E91-D, No.10, pp. 2386-2397(2008)
  24. Masanori Hariyama, Shota Ishihara, Michitaka Kameyama, "Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture", IEICE Trans. Elec. Vol.E91-C,No.9, pp.1419-1426(2008)
  25. Hasitha Muthumala Waidyasooriya, Chong Wei Sheng, Masanori Hariyama, Michitaka Kameyama, "Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment",IEICE Trans. Electron., Vol.E91-C, No.4, pp.517-525,April(2008)
  26. Masanori HARIYAMA, Naoto YOKOYAMA, Michitaka KAMEYAMA, "Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling", IEICE Trans. Electron., Vol.E91-C, No.4, pp.479-486,April(2008)
  27. Masanori HARIYAMA, Sho OGATA, Michitaka KAMEYAMA, "A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates", IEICE Trans. Electron., VOL.E89-C, No.11,pp.1655-1661(2006)
  28. Masanori HARIYAMA, Shigeo YAMADERA, Michitaka KAMEYAMA,"Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification", IEICE Trans. Electron., VOL.E89-C, No.11,pp.1551-1558(2006)
  29. Weisheng Chong,Masanori Hariyama, Michitaka Kameyama, "Low-Power Field-Programmable VLSI Using Multiple Supply Voltages", IEICE Trans. Fundamentals, Vol. E88-A, No.12, pp.3298-3305(2005)
  30. Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, Michitaka Kameyama, "FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture", IEICE Trans. Fundamentals, Vol.E88-A, No.12, pp.3516-3522(2005)
  31. Masanori Hariyama, Haruka Sasaki, and Michitaka Kameyama, "Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access", IEICE Trans. Inf. & Syst., Vol. E88-D, No.7,pp.1486-1491(2005)
  32. Masanori Hariyama, Tetsuya Aoyama, and Michitaka Kameyama, "Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages",IEEE Transaction on Computers, Vol.54, No.6, pp.642-650(2005)
  33. Masanori Hariyama, Weisheng Chong, Michitaka Kameyama,"Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture", IEICE Trans. Electron, Vol.E87-C, No.11, pp.1897-1902(2004)
  34. Michitaka Kameyama, Masanori Hariyama, "Design Methodology for Human-Oriented Intelligent Integrated Systems", Interdisciplinary Information Sciences, Vol.7,No.2,pp.279-287(2001)
  35. Masanori Hariyama, Michitaka Kameyama, "Pixel-Serial and Window-Parallel VLSI Processor for Stereo Matching Using a Variable Window Size, Interdisciplinary Information Sciences, Vol.7,No.2,pp.289-297(2001)
  36. Hideki Kazama, Masanori Hariyama, Michitaka Kameyama, "Design of a VLSI Processor Based on an Immediate Output Generation Scheduling for Ball-Trajectory Prediction", Journal of Robotics and Mechatronics, Vol.12,No.5,pp.534-540(2000)
  37. Masanori Hariyama, Michitaka Kameyama, "Path Planning VLSI Processor Based on Distance Transformation and Its VLSI Implementation", Journal of Robotics and Mechatronics, No.12, Vol.5,pp.527-533(2000)
  38. Masanori Hariyama, Michitaka Kameyama, "Stereo Vision VLSI Processor Based on Pixel-Serial and Window-Parallel Architecture", Journal of Robotics and Mechatronics, No.12,Vol.5, pp.521-526(2000)
  39. Seunghwan Lee, Masanori Hariyama, Michitaka Kameyama,"An FPGA-Oriented Motion-Stereo Processor with a Simple Interconnection Network for Parallel Memory Access", IEICE Trans. INF. Syst., Vol.E83-D, No.12,pp.2122-2130(2000) pp.1722-1729(1999)
  40. Masanori Hariyama, Michitaka Kameyama,"Collision Detection VLSI Processor for Highly-Safe Intelligent Vehicles Using a Multiport Content-Addressable Memory" Interdisciplinary Information Sciences, Vol. 5, No.2, pp.109-115(1999)
  41. Seunghwan Lee, Masanori Hariyama, Michitaka Kameyama, "A Three-Dimensional Instrumentation VLSI Processor Based on a Concurrent Memory-Access Scheme", IEICE Trans. Electron, Vol.E80-C, No.11, pp.1491-1498(1997)
  42. Masanori Hariyama, Michitaka Kameyama,"Design of a CAM-Based Collision Detection VLSI Processor for Robotics",IEICE Trans. Electron,Vol.E77-C,No.7,pp.1108-1115(1994)
  43. Masanori Hariyama, Michitaka Kameyama, "Collision Detection Processor for Intelligent Vehicles",IEICE Trans. Electron, Vol.E76-C1,No.12,pp.1804-1811(1993)