Why FPGA Custom Supercomputing?
AI, optimization, robotics, and scientific simulation require rapidly increasing amounts of computation. Generative AI and digital twins further highlight the need for high-performance computing platforms that are also energy efficient.
We use FPGA, Field Programmable Gate Array, technology to build computing circuits tailored to each problem. By designing the computation itself, rather than only writing software for a fixed processor, we aim to achieve performance and efficiency that are difficult for conventional CPUs and GPUs.
Computing Resources in the AI Era
Large language models, vision transformers, digital twins, and real-time robot control all require large-scale computation and data movement. Simply adding more servers is not a sustainable solution because power consumption and memory access become major bottlenecks.
FPGAs can implement only the circuits needed for a target application, reducing unnecessary operations and improving energy efficiency.
What Is an FPGA?
CPUs are flexible general-purpose processors, while GPUs are powerful for massive parallel computation. FPGAs are different: their circuit structure can be reconfigured to match the computation.
This makes it possible to design arithmetic units, pipelines, memory paths, and data reuse structures specifically for the target algorithm.
Accelerators for Next-Generation AI Models
Recent AI architectures such as Vision Transformer, Vision Mamba, and MLP-Mixer achieve high accuracy but require substantial computation and memory access.
We develop FPGA accelerators that combine temporal parallelism, spatial parallelism, and data reuse. This enables high-throughput AI processing while reducing external memory access and power consumption.
Quantum Annealing Simulation on FPGA
Logistics, scheduling, and placement problems often involve enormous numbers of candidate solutions. We implement quantum annealing simulation on FPGAs to explore such optimization problems at high speed and low power.
Many spin states can be updated in parallel inside the FPGA, and multiple FPGAs can be connected to scale the system for larger problems.
Multi-Robot Path Optimization
In warehouses and factories, many mobile robots must move efficiently without collisions. Fast path planning and real-time replanning are essential.
We apply the idea of Network-on-Chip to represent a workspace inside an FPGA. Robots are modeled as packets moving through a parallel network, enabling fast simulation, collision avoidance, and route optimization.
Future Perspective
Our aim is not limited to developing individual accelerators. We are working toward an integrated computing platform that brings together AI accelerators, optimization engines, quantum annealing simulators, and robot simulation technologies.
By connecting FPGA clusters with digital twins of real-world systems, we hope to create computing infrastructure for prediction, optimization, and control in factories, logistics, robotics, and social infrastructure.