60. Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama and Michitaka Kameyama, "Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators", IEICE Transaction on Fundamentals, Vol.E98-A,No.12,pp.2658-2669(2015)
59. Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yasuhiro Takei, and Michitaka Kameyama, "FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation," Journal of Computational Engineering, vol. 2014, Article ID 634269, (2014).
doi:10.1155/2014/634269
58. Zhengfan Xia, Masanori Hariyama, and Michitaka Kameyama, "Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path", IEEE Transaction on VLSI Systems, Vol.23, No. 4, pp.619-630(2015).
doi:10.1109/TVLSI.2014.2314685
57. Yasuhiro Takei, Hasitha Muthumala WAIDYASOORIYA, Masanori Hariyama, Michitaka Kameyama, "Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators", IEICE Transaction on Information and Systems, Vol.E96-A,No.12,pp.2576-2586 (2013)
56. Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama, "Architecture of an Asynchronous FPGA for Handshake-Component-Based Design", IEICE Transaction on Information and Systems, Vol.E96-D, No.8, pp.1632-1644(2013)
55. SHOTA ISHIHARA, NORIAKI IDOBATA, MASANORI HARIYAMA AND MICHITAKA KAMEYAMA, "Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures", Journal of Multiple-Valued Logic and Soft Computing, Vol.20, No.5-6, pp.595-623(2013)
54. Yoshitaka HIRAMATSU, Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Toru NOJIRI, Kunio UCHIYAMA, and Michitaka KAMEYAMA, "Acceleration of Block Matching on a Low-power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-allocation", IEICE Trans. Elec. VOL.E95-C,No.12, pp.1872-1882,No.(2012)
53. Masanori HARIYAMA, Hasitha muthumala waidyasooriya, Yasuhiro TAKEI, and Michitaka KAMEYAMA, "Platform and Mapping Methodology for Heterogeneous Multicore Processors", Interdisciplinary Information Sciences, Vol. 18, No. 2,pp.175-184 (2012)
52. Xia Zhengfan, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama,"Design of High-performance Asynchronous Pipeline Using Synchronizing Logic Gates", IEICE Transaction on Electron,VOL.E95-C, No.8, pp.1434-1443(2012)
51. Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama, "Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors",IEICE Trans. Inf. and Syst.,Vol.E95-D, No.2,pp.354-363(2012)
50. Shota ISHIHARA Ryoto TSUCHIYA Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA, "Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture", IEICE Transaction on Electron., Vol.E-94-C, No.10, pp.1669-1679, October(2011)
49. Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama,and Michitaka Kameyama, "Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors", IEEE Transactions on Circuits and Systems for Video Technology, Vol.21, No. 10, pp.1453-1466 (2011)
48.Shota Ishihara, Masanori Hariyama, Michitaka Kameyama, "A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating", IEEE Transactions on Very Large Scale Integration Systems, Vol. 19, No. 8, pp.1394-1406 (2011)
47. Shota Ishihara, Noriaki Idobata, Yoshihiro Nakatani, Masanori Hariyama and Michitaka Kameyama, "A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals", Journal of Multiple-Valued Logic and Soft Computing, Vol. 17, No.5-7, pp.553-580(2011)
46. Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama, "Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions", IEICE Transaction on Fundamentals, Vol.E94-A,No.1,pp.pp.342-351(2011)
45. Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama, "Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation", IEICE Transaction on Fundamentals, VOL. E93-A, No. 12(2010)
44. Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama,"Evaluation of a Self-Adaptive Voltage Control Scheme for Low-Power FPGAs",Journal of Semiconductor Technology and Science (JSTS), Vol. 10, No. 3, pp.165-175, 2010.
43. Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama, "An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture", IEICE Transactions on Electronics, Vol. E93-C, No. 8(Aug.),pp.1338-1348(2010)
42. Shota Ishihara, Noriaki Idobata, Masanori Hariyama,Michitaka Kameyama, "A Switch Block Architecture for Multi-Context FPGAs Based on Ferroelectric-Capacitor Functional Pass- Gate Using Multiple/Binary Valued Hybrid Signals", IEICE Transaction on Information and Systems, Vol. E93-D, No. 8(Aug.), pp.2134-2144(2010)
41.[Letter] Z. Xia, S. Ishihara, M. Hariyama, M. Kameyama, "Synchronising logic gates for wave-pipelining design", Electronics Letters, Vol. 46, No. 16, pp. 1116-1117(2010).
40. Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA and Michitaka KAMEYAMA, "Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture", IEICE Transaction on Electron., Vol.E92-C, No.4, pp.539-549(2009)
39. Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyamaa, "Optimal Periodic Memory Allocation for Image Processing with Multiple Windows", IEEE Trans. VLSI Systems, Vol.17, No, 3, pp.403-416(2009)
38. Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA and Michitaka KAMEYAMA, "Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages", IEICE Transaction on Fundamentals, VOL.E91-A, No12, pp.3596-3606(2008)
37. Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama, "Memory Allocation for Multi-Resolution Image Processing", IEICE Transaction on Information and Systems, Vol.E91-D, No.10, pp. 2386-2397(2008)
36. Masanori Hariyama, Shota Ishihara, Michitaka Kameyama, "Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture", IEICE Trans. Elec. Vol.E91-C,No.9, pp.1419-1426(2008)
35. Hasitha Muthumala Waidyasooriya, Chong Wei Sheng, Masanori Hariyama, Michitaka Kameyama, "Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment",IEICE Trans. Electron., Vol.E91-C, No.4, pp.517-525,April(2008)
34. Masanori HARIYAMA, Naoto YOKOYAMA, Michitaka KAMEYAMA, "Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling", IEICE Trans. Electron., Vol.E91-C, No.4, pp.479-486,April(2008)
33. 小林康浩，張山昌論, 亀山充隆, "ウィンドウ演算のための最適スケジューリング・メモリアロケーション", 電子情報通信学会論文誌, Vol.J90-D, No. 5, pp.1178-1193(2007)
32. Masanori HARIYAMA, Sho OGATA, Michitaka KAMEYAMA, "A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates", IEICE Trans. Electron., VOL.E89-C, No.11,pp.1655-1661(2006)
31. Masanori HARIYAMA, Shigeo YAMADERA, Michitaka KAMEYAMA,"Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification", IEICE Trans. Electron., VOL.E89-C, No.11,pp.1551-1558(2006)
30. Weisheng Chong,Masanori Hariyama, Michitaka Kameyama, "Low-Power Field-Programmable VLSI Using Multiple Supply Voltages", IEICE Trans. Fundamentals, Vol. E88-A, No.12, pp.3298-3305(2005)
29. Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, Michitaka Kameyama, "FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture", IEICE Trans. Fundamentals, Vol.E88-A, No.12, pp.3516-3522(2005)
28. Masanori Hariyama, Haruka Sasaki, and Michitaka Kameyama, "Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access", IEICE Trans. Inf. & Syst., Vol. E88-D, No.7,pp.1486-1491(2005)
27. Masanori Hariyama, Tetsuya Aoyama, and Michitaka Kameyama, "Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages",IEEE Transaction on Computers, Vol.54, No.6, pp.642-650(2005)
26. Masanori Hariyama, Weisheng Chong, Michitaka Kameyama,"Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture", IEICE Trans. Electron, Vol.E87-C, No.11, pp.1897-1902(2004)
25. 張山昌論，竹内俊樹，亀山充隆,"最適スケジューリングに基づくステレオビジョンVLSIプロセッサの構成",電子情報通信学会論文誌,Vol.J87-A,No.5,pp.672-680(2004)
24. 工藤隆雄, 張山昌論, 亀山充隆,"遺伝的アルゴリズムを用いたロジックインメモリVLSIプロセッサのハイレベルシンセシス", 情報処理学会論文誌, Vol.44,No.5,pp.1206-1215(2003)
23. 三浦清志,張山昌論,亀山充隆,"再帰的計算に基づくステレオマッチングとVLSI化", 電子情報通信学会論文誌, Vol.J86-C,No.8,pp.752-759(2003)
22. 張山昌論, 風間英樹, 亀山充隆,"階層的並列メモリアクセスに基づくボール軌道予測用VLSIプロセッサの構成", 電子情報通信学会論文誌, Vol.J86-C,No.8,pp.760-770(2003)
21. 張山昌論，工藤隆雄，亀山充隆,"ウィンドウ演算のための周期的メモリアロケーションと画像処理VLSIプロセッサへの応用",電子情報通信学会論文誌, Vol.J86-C,No.5,pp.524-533(2003)
20. 張山昌論,竹内俊樹,亀山充隆, "ウィンドウサイズの適応的選択に基づく高信頼ステレオマッチングアルゴリズムとVLSI化", 計測自動制御学会論文集,Vol.39,No.3,pp.225-233(2003)
19. 大澤尚学, 張山昌論, 亀山充隆, "コントロール／データフローグラフの直接アロケーションに基づくフィールドプログラマブルVLSIプロセッサ", 電子情報通信学会論文誌, Vol.J85-C, No.5,pp.384-392(2002)
18. Michitaka Kameyama, Masanori Hariyama, "Design Methodology for Human-Oriented Intelligent Integrated Systems", Interdisciplinary Information Sciences, Vol.7,No.2,pp.279-287(2001)
17. Masanori Hariyama, Michitaka Kameyama, "Pixel-Serial and Window-Parallel VLSI Processor for Stereo Matching Using a Variable Window Size, Interdisciplinary Information Sciences, Vol.7,No.2,pp.289-297(2001)
16. 張山昌論, 工藤隆雄, 亀山充隆,"最適アロケーションに基づく道路抽出VLSIプロセッサとその高安全知能自動車への応用",電子情報通信学会論文誌,Vol.J84-D-I,No.6,pp.531-539(2001)
15. 張山昌論, 亀山充隆,"障害物の階層的表現に基づく高安全自動車用衝突チェックVLSIプロセッサの設計", 電気学会論文誌,Vol.121-C,No.6,pp.1016-1025(2001)
14. 張山昌論, 山口文武, 亀山充隆,"読み出し専用連想メモリを用いた超高速軌道計画VLSIプロセッサの試作",計測自動制御学会論文集,Vol.37,No.3,pp.235-241(2001)
13. Masanori Hariyama, Seunghwan Lee, Michitaka Kameyama,"Highly-Parallel Stereo Vision VLSI Processor Based on an Optimal Parallel Memory Access Scheme",IEICE Trans. Electron, Vol.E84-C,No.3,pp.382-389(2001)
12. Hideki Kazama, Masanori Hariyama, Michitaka Kameyama, "Design of a VLSI Processor Based on an Immediate Output Generation Scheduling for Ball-Trajectory Prediction", Journal of Robotics and Mechatronics, Vol.12,No.5,pp.534-540(2000)
11. Masanori Hariyama, Michitaka Kameyama, "Path Planning VLSI Processor Based on Distance Transformation and Its VLSI Implementation", Journal of Robotics and Mechatronics, No.12, Vol.5,pp.527-533(2000)
10. Masanori Hariyama, Michitaka Kameyama, "Stereo Vision VLSI Processor Based on Pixel-Serial and Window-Parallel Architecture", Journal of Robotics and Mechatronics, No.12,Vol.5, pp.521-526(2000)
09. Seunghwan Lee, Masanori Hariyama, Michitaka Kameyama,"An FPGA-Oriented Motion-Stereo Processor with a Simple Interconnection Network for Parallel Memory Access", IEICE Trans. INF. Syst., Vol.E83-D, No.12,pp.2122-2130(2000)
08. 張山昌論, 李昇桓, 亀山充隆,"転送ボトルネックのないセンサ・メモリアーキテクチャに基づくモーションステレオVLSIプロセッサの構成", 電気学会論文誌,Vol.120-E,No.5,pp.237-243(2000)
07. 張山昌論, 佐々木和宏, 亀山充隆,"Collision Detection VLSI Processor for Intelligent Vehicles Using a Hierarchically-Content-Addressable Memory", IEICE Trans. Electron, Vol.E82-C, No.9, pp.1722-1729(1999)
06. Masanori Hariyama, Michitaka Kameyama,"Collision Detection VLSI Processor for Highly-Safe Intelligent Vehicles Using a Multiport Content-Addressable Memory" Interdisciplinary Information Sciences, Vol. 5, No.2, pp.109-115(1999)
05. Seunghwan Lee, Masanori Hariyama, Michitaka Kameyama, "A Three-Dimensional Instrumentation VLSI Processor Based on a Concurrent Memory-Access Scheme", IEICE Trans. Electron, Vol.E80-C, No.11, pp.1491-1498(1997)
04. 張山昌論, 荒海雄一, 亀山充隆,"３次元物体直方体表現用ロボットビジョンVLSIプロセッサ",電子情報通信学会論文誌,Vol.J79-D-I.No.5,pp.245-252(1996)
03. 張山昌論, 亀山充隆,"読出し専用型連想メモリに基づく高安全自動車用衝突チェックVLSIプロセッサ"電子情報通信学会論文誌,Vol.J79-C-II,No.11,pp.698-705(1996)
02. Masanori Hariyama, Michitaka Kameyama,"Design of a CAM-Based Collision Detection VLSI Processor for Robotics",IEICE Trans. Electron,Vol.E77-C,No.7,pp.1108-1115(1994)
01. Masanori Hariyama, Michitaka Kameyama, "Collision Detection Processor for Intelligent Vehicles",IEICE Trans. Electron, Vol.E76-C1,No.12,pp.1804-1811(1993)