Journal Papers
1. Masanori Hariyama, Michitaka Kameyama, "Collision Detection Processor for Intelligent Vehicles",IEICE Trans. Electron, Vol.E76-C1,No.12,pp.1804-1811(1993)
2. Masanori Hariyama, Michitaka Kameyama,"Design of a CAM-Based Collision Detection VLSI Processor for Robotics",IEICE Trans. Electron,Vol.E77-C,No.7,pp.1108-1115(1994) 3. Seunghwan Lee, Masanori Hariyama, Michitaka Kameyama, "A Three-Dimensional Instrumentation VLSI Processor Based on a Concurrent Memory-Access Scheme", IEICE Trans. Electron, Vol.E80-C, No.11, pp.1491-1498(1997) 4. Masanori Hariyama, Michitaka Kameyama,"Collision Detection VLSI Processor for Highly-Safe Intelligent Vehicles Using a Multiport Content-Addressable Memory" Interdisciplinary Information Sciences, Vol. 5, No.2, pp.109-115(1999) 5. Seunghwan Lee, Masanori Hariyama, Michitaka Kameyama,"An FPGA-Oriented Motion-Stereo Processor with a Simple Interconnection Network for Parallel Memory Access", IEICE Trans. INF. Syst., Vol.E83-D, No.12,pp.2122-2130(2000) 6. Masanori Hariyama, Michitaka Kameyama, "Stereo Vision VLSI Processor Based on Pixel-Serial and Window-Parallel Architecture", Journal of Robotics and Mechatronics, No.12,Vol.5, pp.521-526(2000) 7. Masanori Hariyama, Michitaka Kameyama, "Path Planning VLSI Processor Based on Distance Transformation and Its VLSI Implementation", Journal of Robotics and Mechatronics, No.12, Vol.5,pp.527-533(2000) 8. Hideki Kazama, Masanori Hariyama, Michitaka Kameyama, "Design of a VLSI Processor Based on an Immediate Output Generation Scheduling for Ball-Trajectory Prediction", Journal of Robotics and Mechatronics, Vol.12,No.5,pp.534-540(2000) 9. Masanori Hariyama, Seunghwan Lee, Michitaka Kameyama,"Highly-Parallel Stereo Vision VLSI Processor Based on an Optimal Parallel Memory Access Scheme",IEICE Trans. Electron, Vol.E84-C,No.3,pp.382-389(2001) 10. Masanori Hariyama, Michitaka Kameyama, "Pixel-Serial and Window-Parallel VLSI Processor for Stereo Matching Using a Variable Window Size, Interdisciplinary Information Sciences, Vol.7,No.2,pp.289-297(2001) 11. Michitaka Kameyama, Masanori Hariyama, "Design Methodology for Human-Oriented Intelligent Integrated Systems", Interdisciplinary Information Sciences, Vol.7,No.2,pp.279-287(2001) 12. Masanori Hariyama, Weisheng Chong, Michitaka Kameyama,"Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture", IEICE Trans. Electron, Vol.E87-C, No.11, pp.1897-1902(2004) 13. Masanori Hariyama, Tetsuya Aoyama, and Michitaka Kameyama, "Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages",IEEE Transaction on Computers, Vol.54, No.6, pp.642-650(2005) 14. Masanori Hariyama, Haruka Sasaki, and Michitaka Kameyama, "Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access", IEICE Trans. Inf. & Syst., Vol. E88-D, No.7,pp.1486-1491(2005) 15.Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, Michitaka Kameyama, "FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture", IEICE Trans. Fundamentals, Vol.E88-A, No.12, pp.3516-3522(2005) 16.Weisheng Chong,Masanori Hariyama, Michitaka Kameyama, "Low-Power Field-Programmalble VLSI Using Multiple Supply Voltages", IEICE Trans. Fundamentals, Vol. E88-A, No.12, pp.3298-3305(2005) 17. Masanori HARIYAMA, Shigeo YAMADERA, Michitaka KAMEYAMA, "Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification", IEICE Trans. Electron., VOL.E89-C, No.11,pp.1551-1558(2006) 18. Masanori HARIYAMA, Sho OGATA, Michitaka KAMEYAMA, "A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates", IEICE Trans. Electron., VOL.E89-C, No.11,pp.1655-1661(2006) 19. Masanori HARIYAMA, Naoto YOKOYAMA, Michitaka KAMEYAMA, "Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling", IEICE Trans. Electron., Vol.E91-C, No.4, pp.479-486,April(2008) 20. Hasitha Muthumala Waidyasooriya, Chong Wei Sheng, Masanori Hariyama, Michitaka Kameyama, "Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment",IEICE Trans. Electron., Vol.E91-C, No.4, pp.517-525,April(2008) 21. Masanori Hariyama, Shota Ishihara, Michitaka Kameyama, "Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture", IEICE Trans. Elec. Vol.E91-C,No.9,pp.1416-1426(2008) 22. Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama, "Memory Allocation for Multi-Resolution Image Processing", IEICE Transaction on Information and Systems, Vol.E91-D, No.10, pp. 2386-2397(2008) 23. Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA and Michitaka KAMEYAMA, "Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages", IEICE Transaction on Fundamentals, VOL.E91-A, No12, pp.3596-3606(2008) 24. Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyamaa, "Optimal Periodic Memory Allocation for Image Processing with Multiple Windows", IEEE Trans. VLSI Systems, Vol.17, No, 3, pp.403-416(2009) 25. Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA and Michitaka KAMEYAMA, "Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture", IEICE Transaction on Electron., Vol.E92-C, No.4, pp.539-549(2009) 26. Z. Xia, S. Ishihara, M. Hariyama, M. Kameyama, "Synchronising logic gates for wave-pipelining design", Electronics Letters, Vol. 46, No. 16, pp. 1116-1117(2010) 27. Shota Ishihara, Noriaki Idobata, Masanori Hariyama,Michitaka Kameyama, "A Switch Block Architecture for Multi-Context FPGAs Based on Ferroelectric-Capacitor Functional Pass- Gate Using Multiple/Binary Valued Hybrid Signals", IEICE Transaction on Information and Systems, Vol. E93-D, No. 8(Aug.), pp.2134-2144(2010) 28. Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama, "An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture", IEICE Transactions on Electronics, Vol. E93-C, No. 8(Aug.),pp.1338-1348(2010) 29. Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama,"Evaluation of a Self-Adaptive Voltage Control Scheme for Low-Power FPGAs", Journal of Semiconductor Technology and Science (JSTS), Vol. 10, No. 3, pp.165-175, 2010. 30. Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama, "Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation", IEICE Transaction on Fundamentals, VOL. E93-A, No. 12(2010) 31. Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama, "Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions", IEICE Transaction on Fundamentals, Vol.E94-A,No.1,pp.pp.342-351(2011) 32.Shota Ishihara, Masanori Hariyama, Michitaka Kameyama, "A Low-Power FPGA Based on Autonomous Fine-Grain Power@Gating", IEEE Transactions on Very Large Scale Integration Systems, Vol. 19, No. 8, pp.1394-1406 (2011) 33. Shota Ishihara, Noriaki Idobata, Yoshihiro Nakatani, Masanori Hariyama and Michitaka Kameyama, "A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals", Journal of Multiple-Valued Logic and Soft Computing, Vol. 17, No.5-7, pp.553-580(1011) 34. Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama,and Michitaka Kameyama, "Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors", IEEE Transactions on Circuits and Systems for Video Technology, Vol.21, No. 10, pp.1453-1466 (2011) 35. Shota ISHIHARA Ryoto TSUCHIYA Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA, "Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture", IEICE Transaction on Electron., Vol.E-94-C, No.10, pp.1669-1679, October(2011) 36. Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama, "Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors",IEICE Trans. Inf. and Syst.,Vol.E95-D, No.2,pp.354-363 (2012) 37. Xia Zhengfan, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama,"Design of High-performance Asynchronous Pipeline Using Synchronizing Logic Gates", IEICE Transaction on Electron,VOL.E95-C, No.8, pp.1434-1443(2012) 38. Masanori HARIYAMA, Hasitha Muthumala WAIDYASOORIYA, Yasuhiro TAKEI, and Michitaka KAMEYAMA, "Platform and Mapping Methodology for Heterogeneous Multicore Processors", Interdisciplinary Information Sciences, Vol. 18, No. 2,pp.175-184 (2012)[PDF] 39. Yoshitaka HIRAMATSU, Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Toru NOJIRI, Kunio UCHIYAMA, and Michitaka KAMEYAMA, "Acceleration of Block Matching on a Low-power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-allocation", IEICE Trans. Elec. VOL.E95-C,No.12, pp.1872-1882,No.(2012) [PDF] 40. SHOTA ISHIHARA, NORIAKI IDOBATA, MASANORI HARIYAMA AND MICHITAKA KAMEYAMA, "Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures", Journal of Multiple-Valued Logic and Soft Computing, Vol.20, No.5-6, pp.595-623(2013)[PDF] 41.Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama, "Architecture of an Asynchronous FPGA for Handshake-Component-Based Design", IEICE Transaction on Information and Systems, Vol.E96-D, No.8, pp.1632-1644(2013) [PDF] 42. Yasuhiro Takei, Hasitha Muthumala WAIDYASOORIYA, Masanori Hariyama, Michitaka Kameyama, "Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators",IEICE Transaction on Fundamentals, IEICE Transaction on Information and Systems, Vol.E96-A,No.12,pp.2576-2586 (2013) [PDF] 43. Zhengfan Xia, Masanori Hariyama, and Michitaka Kameyama, "Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path", IEEE Transaction on VLSI Systems (To be published) 44. Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yasuhiro Takei, and Michitaka Kameyama, "FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation," Journal of Computational Engineering, vol. 2014, Article ID 634269, (2014). [PDF] doi:10.1155/2014/634269 45. Zhengfan Xia, Masanori Hariyama, and Michitaka Kameyama, "Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path", IEEE Transaction on VLSI Systems, Vol.23, No. 4, pp.619-630(2015).[PDF] doi:10.1109/TVLSI.2014.2314685 46. Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama and Michitaka Kameyama, "Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators", IEICE Transaction on Fundamentals, Vol.E98-A,No.12,pp.2658-2669(2015) [PDF] 47. Hasitha Muthumala Waidyasooriya, Daisuke Ono and Masanori Hariyama, "Hardware-Oriented Succinct-Data-Structure for Text Processing Based on Block-Size-Constrained Compressionh, International Journal of Computer Information Systems and Industrial Management Applications, Vol.8, pp.1-11(2016) [PDF] 48. "Hardware-Acceleration of Short-read Alignment Based on the Burrows-Wheeler Transform", Hasitha Muthumala Waidyasooriya and Masanori Hariyama, IEEE Transactions on Parallel and Distributed Systems, Vol. 27, No. 5, pp. 1358-1372, May 1 (2016). (2015) [PDF] DOI:10.1109/TPDS.2015.2444376 International Conference
91. Hasitha Waidyasooriya, Daisuke Ono and Masanori Hariyama, "Hardware-Oriented Succinct-Data-Structure based on the Block-Size-Constrained Compression", Proc. SoCPaR 2015, pp.136-140(2015) [PDF]
90. Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama, Michitaka Kameyama, "An FPGA Architecture for Text Search Using a Wavelet-Tree-Based Succinct-Data-Structure", International Conference on Parallel and Distributed Processing Techniques and Applications(PDPTA), pp.354-359,(2015-07-28, Las Vegas, Nevada, USA) [PDF] 89. Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama,"FPGA-Oriented Design of an FDTD Accelerator Based on Overlapped Tiling",International Conference on Parallel and Distributed Processing Techniques and Applications(PDPTA), pp.72-77 (2015-07-29, Las Vegas, Nevada, USA) [PDF] 88. Shunsuke Tatsumi, Masanori Hariyama, Mamoru Miura, Koichi Ito, Takafumi Aoki,"OpenCL-based Design of an FPGA Accelerator for Phase-Based Correspondence Matching", Proc. International Conference on Parallel and Distributed Processing Techniques and Applications(PDPTA) pp.613-617 (2015-07-28, Las Vegas, Nevada, USA) [PDF] 87. Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama, "Evaluation of an FPGA-Based Shortest-Path-Search Accelerator", International Conference on Parallel and Distributed Processing Techniques and Applications(PDPTA) pp.613-617 (2015-07-29, Las Vegas, Nevada, USA) [PDF] 86. Masanori Hariyama, Takeaki Suzuki, Keisuke Maeda, Mitsugi Shimoda, Keiichi Kubota,"Automatic Estimation of Optimal Resected Liver Regions Considering Practical Surgical Conditions", Proc.International Conference on Image Processing, Computer Vision, and Pattern Recognition(IPCV),pp.356-360(2015-07-29, Las Vegas, Nevada, USA) [PDF] 85. Yasuhiro Kobayashi, Masanori Hariyama, Mitsugi Shimoda, Keiichi Kubota,"Accurate Liver Extraction Using a Local-Thickness-Based Graph-Cut Approach", Proc.International Conference on Image Processing, Computer Vision, and Pattern Recognition(IPCV),pp.315-318(2015-07-29, Las Vegas, Nevada, USA) [PDF] 84. Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama and Michitaka Kameyama, "Efficient Data Transfer Scheme Using Word-Pair-Encoding-Based Compression for Large-Scale Text-Data Processing", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp.639-642(2014-11-19,Okinawa,Japan)[PDF] 83. Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama, "An SIMD Architecture for Shortest-Path Search and Its FPGA Implementation", Proc. International Conference on Parallel and Distributed Processing Techniques and Applications(PDPTA), pp.53-56, (2014-07-24, Las Vegas, Nevada, USA, regular). [PDF] 82. Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama,Michitaka Kameyama,"Design of an FPGA-Based FDTD Accelerator Using OpenCL", Proc. International Conference on Parallel and Distributed Processing Techniques and Applications(PDPTA), pp.371-375, (2014-07-23, Las Vegas, Nevada, USA, regular). [PDF] 81. Masanori Hariyama, Riichi Tanizawa, Mitsugi Shimoda, Keiichi Kubota, Yasuhiro Kobayashi, "Liver Extraction from CT Images Based on Liver Structure Models", Proc.International Conference on Image Processing, Computer Vision, and Pattern Recognition(IPCV), pp.170-173, (2014-07-23, Las Vegas, Nevada, USA, regular). [PDF] 80.Masanori Hariyama, Moe Okada, Mitsugi Shimoda, Keiichi Kubota, "Estimation of Resected Liver Regions Using a Tumor Domination Ratio", Proc.International Conference on Image Processing, Computer Vision, and Pattern Recognition(IPCV), pp.52-56, (2014-07-22, Las Vegas, Nevada, USA, regular). [PDF] 79. Hasitha Waidyasooriya, Masanori Hariyama and Michitaka Kameyama,"FPGA-Accelerator for DNA Sequence Alignment Based on an Efficient Data-Dependent Memory Access Scheme",Proc. the 5th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies(HEART), pp.127-130,(2014-06-10, Sendai, poster). [PDF] 78. Yoshiya Komatsu, Masanori Hariyama and Michitaka Kameyama, "An Asynchronous High-Performance FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture", Proc. the 5th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), pp.111-114(2014-06-10, Sendai,poster)[PDF] 77. Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama, "A Low-Power FPGA Based on Self-Adaptive Multi-Voltage Control", Proc. International SoC Design Conference (ISOCC), pp. 166-169, (2013-11-19). [PDF] 76. Yoshiya KOMATSU, Masanori HARIYAMA and Michitaka KAMEYAMA, "An Area-Efficient Asynchronous FPGA Architecture for Handshake-Component-Based Design", Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), pp. 15-18,July 2013 [PDF] 75. Hasitha Muthumala Waidyasooriya, Hirokazu Takahashi, Yasuhiro Takei, Masanori Hariyama and Michitaka Kameyama,"Reducing Floating-Point Error Based on Residue-Preservation and Its Evaluation on an FPGA", Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), pp.55-58, July 2013. [PDF] 74. Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama and Michitaka Kameyama,"Heterogeneous Multicore Platform with Accelerator Templates and Its Implementation on an FPGA with Hard-core CPUs", Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), pp.47-50, July 2013. [PDF] 73. Hasitha Muthumala Waidyasooriya, Masanori Hariyama and Michitaka Kameyama,"Implementation of a Custom Hardware-Accelerator for Short-read Mapping Using Burrows-Wheeler Alignment",Proc. 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBS) ,pp.651-654(2013).[PDF] 72. Yoshiya KOMATSU, Masanori HARIYAMA and Michitaka KAMEYAMA, "Architecture of an Asynchronous FPGA for Handshake-Component-Based Design", Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), pp.133-136,July 2012.[PDF] 71. Yoshiya KOMATSU, Masanori HARIYAMA and Michitaka KAMEYAMA, "Area-Efficeint Design of Asynchronous Circuits Based on Balsa Framework for Synchronous FPGAs", Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA),pp.113-118 July 2012.[PDF] 70.Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama and Michitaka Kameyama, "Hybrid Single/Double Precision Floating-Point Computation on GPU Accelerators for 2-D FDTD", International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), pp.1001-1002(July 2012). [PDF] 69.Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama,"Low-Power Heterogeneous Platform for High Performance Computing and Its Application to 2D-FDTD Computation", Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), pp.147-150(July 2012). [PDF] 68.Zhengfan XIA, Shota ISHIHARA, Masanori HARIYAMA, and Michitaka KAMEYAMA, "An Asynchronous FPGA Based on Dual/Single-Rail Hybrid Architecture", Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA),pp.139-142(July 2012). [PDF] 67. Zhengfan Xia, Shota Ishihara, Masanori Hariyama, and Michitaka Kameyama, "Dual-Rail/Single-Rail Hybrid Logic Design for High-Performance Asynchronous Circuit" IEEE International Symposium on Circuits and Systems, pp.3017-3020, May 2012. 66. Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama, "FPGA Implementation of Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators", IEEE International Symposium on Circuits and Systems(ISCAS), pp.1339-1342,2012-5-22 65. (No refree) Yoshiya Komatsu, Masanori Hariyama, Shota Ishihara, Ryoto Tsuchiya, Michitaka Kameyama, "An Architecture of a Synchronous / Asynchronous Hybrid FPGA", The 4th Student-Organizing International Mini-Conference on Information Electronics Systems (SOIM), 274-275(2012-02-23) 64. (No refree) Z. Xia, S. Ishihara, M. Hariyama and M. Kameyama gA Design Method of High-Performance Asynchronous Pipeline,h Student Organizing International Mini-Conference on Information Electronics Systems (SOIM), pp. 276-277(2012-2-23). 63. Masanori Hariyama, Yoshiya Komatsu, Shota Ishihara, Ryoto Tsuchiya, and Michitaka Kameyama, "An FPGA Based on Synchronous/Asynchroous Hybrid Architecture with Area-Efficient FIFO Interfaces", Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), pp. 331-334(2011-07-19) 62. Yosuke Ohbayashi, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama, "Data-Transfer-Aware Memory Allocation for Dynamically Reconfigurable Accelerators in Heterogeneous Multicore Processors", Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), pp. 282-288(2011-07-18) 61.Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama, "An Implementation of an Asynchronous FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture" , Proceedings of The Asia and South Pacific Design Automation Conference (ASP-DAC), pp.89-90, Jan, 26, 2011 60. (No refree) Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama, "Implementation of a Low-Power FPGA Based on Self-Adaptive Voltage Control", Student Organizing International Mini-Conference on Information Electronics Systems (SOIM), pp. 57-58, 2010. 59. (Invited Talk) (No refree) Hasitha Muthumala Waidyasooriya, Masanori Hariyama, and Michitaka Kameyama, "Accelerator-Centric Mapping Methodologies for Heterogeneous Multicore Processors", Integrated Circuits and Devices in Vietnam(ICDV) 2010, pp.49-54, Ho Chi Minh City, Vietnam, August16-18 (2010) 58. Masanori Hariyama, Ryoto Tsuchiya, Shota Ishihara, and Michitaka Kameyama, "An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture", Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA), pp.271-274 , Las Vegas, Nevada, USA, July 12-15(2010) 57. Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, and Michitaka Kameyama, "Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time",Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA), pp.281-282, Las Vegas, Nevada, USA, July 12-15(2010) 56. (Distinguished Paper) Hasitha Muthumala Waidyasooriya, Masanori Hariyama, and Michitaka Kameyama "Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores", Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA), pp.179-186, Las Vegas, Nevada, USA, July 12-15(2010) 55. Shota Ishihara, Zhengfan Xia, Masanori Hariyama, and Michitaka Kameyama, "Architecture of a Low-Power FPGA Based on Self-Adaptive Voltage Control", Proc. International SoC Design Conference (ISOCC), Busan, Nov. 2009, pp.274-277. 54. (No Refree) Michitaka Kameyama and Masanori Hariyama,"Interconnect-Aware High-Level Design Methodologies For Low-Power VLSIs",The 12th International Symposium on Wireless Personal Multimedia Communications (WPMCf09),Stick(2009). (Invited paper) 53. (No Refree) M. Kameyama and M. Hariyama,"Interconnect-Aware High-Level Design Methodologies for Low-Power VLSIs", Proc. of the 3rd International Symposium on Information Electronics Systems, pp.102-105(2009). 52. Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama,"An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters", Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA),pp.145-150 (2009) 51. Masanori Hariyama, Keita Tanji, and Michitaka Kameyama, "FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation", Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA), pp.263-266 (2009) 50. Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama,"A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic", Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA), pp.271-274 (2009) 49. Hasitha Muthumala Waidyasooriya, Masanori Hariyama and Michitaka Kameyama,"Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays", Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA), pp.291-294 (2009) 48. Shota Ishihara, Masanori Hariyama, and Michitaka Kameyama, "A Low-Power FPGA Based on Autonomous Fine-Grain Power-Gating", Asia and South Pacific Design Automation Conference (ASP-DAC), pp.119-120(2009) 47. Masanori Hariyama, Shota Ishihara, and Michitaka Kameyama, "A Low-Power Field-Programmable VLSI Based on a Fine-Grained Power-Gating Scheme", IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp.702-705(2008) 46. Masanori Hariyama, Hisashi Yoshida, Michitaka Kameyama, Yasuhiro Kobayashi, "Image Processing VLSI Architecture Based on Data Compression", IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp.430-433(2008) 45. Waidyasooriya Hasitha Muthumala, Masanori Hariyama, Michitaka Kameyama, "Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning",International Conference on Engineering of Reconfigurable Systems and Algorithms, pp. 201-207(2008) 44. Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama, "Non-volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals", International Conference on Engineering of Reconfigurable Systems and Algorithms, pp.309-310(2008) 43. (No refree) M. Kameyama and M. Hariyama,"Fine-Grained Low-Power Reconfigurable VLSI for Real-World Applications", Proc. of the 2nd Internationa Symposiumu on Information Electronics Systems, pp.96-99(2008). 42. Masanori Hariyama, Kensaku Yamashita and Michitaka Kameyama,"FPGA Implementation of a Vehicle DetectionAlgorithm Using Three-Dimensional Information", Reconfigurable Architectures Workshop, CR-ROM, (2008) 41. Waidyasooriya Hasitha Muthumala, Masanori Hariyama, Michitaka Kameyama, "Design of a Multi-Context FPVLSI based on an Asynchronous Bit-Serial Architecture", Sixth IEEE Dallas circuits and systems workshop, pp.59-62 (2007) 40. Masanori Hariyama, Shota Ishihara, Chang Chia Wei and Michitaka Kameyama, "A Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture", IEEE Asian Solid-State Circuits Conference(A-SSCC), pp.380-383(2007) 39. Waidyasooriya Hasitha Muthumala, Masanori Hariyama, Michitaka Kameyama, "GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design", IEEE Asia Pacific Conference on Circuits and Systems(APCCAS), pp.1266-1269(2006) 38. Masanori Hariyama, Michitaka Kameyama,"A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment", IEEE Asia Pacific Conference on Circuits and Systems(APCCAS),pp.1805-1808(2006) 37. Masanori Hariyama, Naoto Yokoyama and Michitaka Kameyama, "1000 frame/sec Stereo Matching VLSI Processor with Adaptive Window-Size Control", Proc. Asian Solid-State Circuits Conference (A-SSCC),pp.123-126(2006) 36. Masanori Hariyama, Waidyasooriya Hasitha Muthumala, Michitaka Kameyama, "Dynamically Reconfigurable Gate Array Based on Fine-Grained Switch Elements and Its CAD Environment", Proc. Asian Solid-State Circuits Conference (A-SSCC), pp.155-158(2006) 35. Sunggae Lee, Masanori Hariyama, Michitaka Kameyama,"Processor Architecture for Road Extraction Based on Projective Transformation", Proc. SICE-ICCAS 2006, pp.1446-1450(2006) 34. Masanori Hariyama, Michitaka Kameyama, "Fine-Grained Architectures for Field-Programmable VLSIs", 15th International Workshop on Post-Binary ULSI Systems, pp.1-5(2006) 33. Yoshihiro NAKATANI, Masanori HARIYAMA and Michitaka KAMEYAMA,"Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals",International Symposium on Multiple-Valued Logic(ISMVL), CD-ROM(2006) 32. Yoshihiro NAKATANI, Masanori HARIYAMA and Michitaka KAMEYAMA,"Architecture of a Multi-Context FPGA Using a hybrid Multiple-Valued/Binary Context Switching Signal",Reconfigurable Architectures Workshop(RAW),CD-ROM(2006) 31. Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi,"Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors", IEEE Computer Society Anual Symposium on VLSI,pp.193-198(2006) 30. Masanori Hariyama, Sho Ogata, Michitaka Kameyama, Yasutoshi Morita, "Design of Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate", IEEE Asian Solid-State Circuits Conference(A-SSCC), pp.421-424(2005) 29. Masanori Hariyama, Sho Ogata, Michitaka Kameyama , "DSP-Specific Field-Programmable VLSI and Its CAD Environment", IEEE International Midwest Symposium on Circuits and Systems, pp.651-654(2005) 28. Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama, "Minimizing Energy Consumption of VLSI Processors Based on Dual-Supply-Voltage Assignment and Interconnection Simplification", IEEE International Midwest Symposium on Circuits and Systems, pp.1867-1870(2005) 27. Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama, Yasuhiro Kobayashi, "FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel@and@Pixel-Parallel Architecture", IEEE International Midwest Symposium on Circuits and Systems, pp.1219-1222(2005) 26. Masanori Hariyama, Weisheng Chong, Sho Ogata and Michitaka Kameyama,"Novel Switch Block Architecture Using Non-Volatile Functional Pass-gate",IEEE Computer Society Annual Symposium on VLSI, pp.46-50(2005) 25. Weisheng CHONG, Sho Ogata, Masanori HARIYAMA and Michitaka KAMEYAMA,"Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory",Proc. International Parallel and Distributed Processing Symposium,CD-ROM(2005) 24. W. Chong, M. Hariyama, and M. Kameyama,"Novel switch-block architecture using reconfigurable context memory for multi-context FPGAs",Proc. International Workshop on Applied Reconfigurable Computing (ARC 2005), pp.99-102(2005) 23. Masanori Hariyama, Haruka Sasaki, and Michitaka Kameyama,"Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access",International Midwest Symposium on Circuits and Systems, pp.245-247(2004) 22. Masanori Hariyama and Michitaka Kameyama,"VLSI Processor for Reliable Stereo Matching Based on Window-Parallel Logic-in-Memory Architecture",Digest of Technical Paper 2004 Symposium on VLSI Circuits VLSI Symposium, pp.166-169(2004) 21. Naotaka Ohsawa, Osamu Sakamoto,Masanori Hariyama, Michitaka Kameyama,"Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure",IEEE Computer Society Annual Symposium on VLSI, pp.258-259(2004) 20. Weisheng Chong, Masanori Hariyama, Michitaka Kameyama,"Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits",IEEE Computer Society Annual Symposium on VLSI, pp.243-250(2004) 19. Kiyoshi Miura, Masanori Hariyama, Michitaka Kameyama,"Stereo Vision VLSI Processor Based on a Recursive Computation Algorithm",SICE Annual Conference, pp.2338-2341(2003) 18. Naotaka Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama,"Chip Design of a Field Programmable VLSI Processor Using Memory-Based Cells",SICE Annual Conference, pp.2225-2229(2003) 17. Michitaka Kameyama and Masanori Hariyama,"VLSI Computing and System Integration for Real-World Applications",2002 International Symposium on New Paradigm VLSI Computing, pp.13-16(2002) 16. Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama,"Architecture of a Field-Programmable VLSI Processor Using Memory-Based Cells",SICE Annual Conference, pp.2370-2373(2002) 15. M.Hariyama, M.Kameyama,"Optical Flow Extraction Based on Reuse of Intermediate Results and VLSI Implementation",SICE Annual Conference, pp.2366-2369(2002) 14. Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama,"High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph",IEEE Computer Society Annual Symposium on VLSI, pp.95-100(2002) 13. Masanori Hariyama, Toshiki Takeuchi, Michitaka Kameyama,"VLSI Processor for Reliable Stereo Matching Based on Adaptive Window-Size Selection",Proc. International Conference on Robotics and Automation, pp.1168-1173(2001) 12. Masanori Hariyama, Toshiki Takeuchi, Michitaka Kameyama,"VLSI-Oriented Algorithm for Reliable Stereo Matching",IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS),Vol.2, pp.625-630(2000) 11. Masanori Hariyama, Hideki Kazama, Michitaka Kameyama,"VLSI Processor for Hierarchical Template Matching and Its Application to a Ball-Catching Robot System",IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS),Vol.2, pp.613-618(2000) 10. Masanori Hariyama, Toshiki Takeuchi, Michitaka Kameyama,"Reliable Stereo Matching for Highly-Safe Intelligent Vehicles and Its VLSI Implementation",IEEE Intelligent Vehicles Symposium, pp.128-133(2000) 09. Michitaka Kameyama, Takahiro Hanyu, Masanori Hariyama,"Innovation Of Intelligent Integrated System Architecture",International Symposium on Future of Intellcetual Integrated Electronics, pp.231 - 247(1999) 08. Masanori Hariyama, Michitaka Kameyama,"Optimal Design of a Parallel VLSI Processor Based on Minimization of Area-Time Products and Its Application",Proc. the Workshop on Synthesis and System Integration of Mixed Technologyies, pp.179-185(1998) 07. Masanori Hariyama, Michitaka Kameyama,"Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products",Proc. IEEE International Conference on Robotics and Automation, pp.3691-3696(1998) 06. Seunghwan Lee, Masanori Hariyama, Michitaka Kameyama,"Design of a VLSI Processor Chip for Three-Dimensional Instrumentation",SICE'97, pp.951-954(1997) 05. Masanori Hariyama, Michitaka Kameyama,"Collision Detection VLSI Processor for Intelligent Vehicles Based on a Hierarchical Obstacle Representation",Proc. IEEE Conference on Intelligent Transportation Systems,CD-ROM, pp.(1997) 04. Seunghwan Lee, Masanori Hariyama, Michitaka Kameyama,"High-Performance VLSI Architecture for Three-Dimensional Instrumentation Based on a New Concurrent Memory-Access Scheme",Proc. IEEE Asia Pacific Conference on Circuits and Systems,Vol.115C-4, pp.951(1996) 03. Masanori Hariyama, Michitaka Kameyama,"Collision Detection VLSI Processor for Intelligent Vehicles Based on Efficient Coordinate Transformation Scheme",Proc. International Conference on Industrial Electronics, Control, Instrumentation, and Automation,Vol.2, pp.755-760(1996) 02. Masanori Hariyama, Takahiro Hanyu, Michitaka Kameyama,"A Collision Detection Multiprocessor for Intelligent Vehicles Using a High-Density CAM",Proc. Intelligent Vehicles Symposium,Vol.2, pp.143-144(1994) 01. Masanori Hariyama, Michitaka Kameyama,"Parallel Collision Detection Processor for Robotics Using a Content-Addressable Memory",Proc. International Conference on Industrial Electronics, Control, Instrumentation, and Automation,Vol.3, pp.1512-1516(1993) Book
1. M.Kameyama and M.Hariyama, "Interconnect-Aware High-Level Design Methodologies for Low-Power VLSIs", in "Towards Green ICT", River Publishers Series in Communications edited by R.Prasad, S.Ohomori and D. Simunic, pp.265-274 (2010).
|